Last update: 31 May 2004
Motorola 68HC812A4 Overview
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compact 112-pin thin quad flat pack
(TQFP) package
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high degree of 68HC11 architecture and
instruction set compatibility
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greatly expanded instruction set includes
powerful DSP and Fuzzy Logic instructions, memory-to-memory transfers,
table lookup, min & max value
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all HC11 addressing modes, plus new
indexed addressing modes, including accumulator offset indexing, and auto
increment/decrement
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typical 30% code-size reduction over
HC11
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high speed operation (8MHz bus speed,
using 16 MHz crystal)
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single chip mode operation using internal
4K EEPROM and 1K SRAM
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expanded mode operation supports up
to 4MB program memory and 1MB data memory
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non-multiplexed address and data buses
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seven programmable chip selects provided
for "glueless" interface to memories and peripherals
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selectable narrow (8-bit) or wide (16-bit)
bus interface
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two SCI ports support any baud rate
to 38.4K bps (using 16 MHz crystal)
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multiple I/O port lines, with programmable
pullup resistors on most pins
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multiple "key wakeup" port lines for
use with keypad (any key pressed wakes up micro)
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serial peripheral interface (SPI) port
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eight input capture/output compare lines
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versatile 8-channel, 16-bit hardware
timer subsystem
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16-bit pulse accumulator
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high speed 8-channel 8-bit analog-to-digital
converters
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single-wire background debug mode (BDM)
for debugging and code loading
Useful 68HC812A4 data:
Here's an
informative article on the 68HC812A4 written by the Seattle Robotics
Society
Technological Arts, Toronto,
Canada
Toll-free: 1-877-963-8996
(USA and Canada) Phone: (416) 963-8996 Fax: (416) 963-9179
www.technologicalarts.com
©2004 Technological Arts
